Signal detection in noisy transmission path

ABSTRACT

Circuit for sensing the presence of a signal on a line preceded by noise on the line, such as noise created by switch bounce. The circuit, which includes flip-flops and logic gates, ignores noise bursts and produces only a single change in direct voltage level at the circuit output terminal, in response to a signal.

United! States Patent Morgan et a1. Mar. 5, 1974 [54] SIGNAL DETECTIONIN NOISY 3,564,429 2/1971 Miller 328/58 TRANSMISSION PATH 3,440,5464/1969 Nelson... 328/58 3,430,148 2/1969 Miki 307/215 Inventors: DavidKeith Morgan, Flemington; 3,327,225 6/1967 Schell 307 215 Robert CharlesHeuner, Bound 3,264,567 8/1966 Prieto 307/215 BIOOk, 130th of NJ.3,287,495 11/1966 Willard 307/218 [73] Assignee: RCA Corporation,Princeton, NJ. Primary Examiner Rudolph V" Rolinec [22] Filed: Nov. 9,1972 Assistant ExaminerR. E. Hart [21] PP No: 304 892 Attorney, Agent,or Firm-H. Christoffersen; Samuel Cohen [52] US. Cl 307/247, 307/215,328/63 [51] Int. Cl. [103k 17/56 [57] ABSTRACT [58] Field f Search3O7/215218, 328/58 Circuit for sensing the presence of a signal on aline 323/94 3 preceded by noise on the line, such as noise created byswitch bounce. The circuit, which includes flip-' 5 References Citedflops and logic gates, ignores noise bursts and pro- UNITED STATESPATENTS ducesonly a single change in direct voltage level at the circuitoutput terminal, in response to a signal. 3,244,986 4/1966 Rumble307/218 3,284,715 11/1966 Kaminsky 328/94 11 Claims, 2 Drawing Figures 0T FF OUTPUT PATENTEDHAR SIGN Fin. 1

SIGNAL DETECTION IN NOISY TRANSMISSION PATH BACKGROUND OF THE INVENTIONThe situation in which both signal and noise may be present on a line iscommon in many electrical systems. An example of particular interest inthe present application is a digital circuit, such as an electronicwatch, in which the momentary closing of a mechanical switch is employedto set the time. At the instant the switch is closed, the bounce of theswitch contacts results in electrical oscillations on the line and it isnot until these die down that a steady direct voltage level remains.These oscillations or other noise must be kept from the digital circuitto prevent undesired eratic operation thereof. In the case of theelectronic watch, for example, where a mechanical switch is employed toset the time, the oscillations would cause the time to advance at anerratic rate corresponding to the switch bounce frequency.Notwithstanding this, the circuit should receive, within a reasonabletime after the switch has been closed, some positive indication thatthis event has occurred.

SUMMARY OF THE INVENTION BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is alogic diagram of a preferred embodiment of the invention; and t FIG. 2is a drawing of waveforms present in the circuit of FIG. 1.

DETAILED DESCRIPTION The circuit of FIG. 1 includes two triggerableflipflops l and 12 and a logic circuit indicated generally by the number14. The state the triggerable flip-flop assumes is controlled by theinformation signal present at its data terminal (D in the case of and Din the case of 12) when a positive-going edge, of the clock signaloccurs. If, at this time, the signal applied to the D terminal isrelatively high, the flip-flop becomes set and if it is relatively low,the flip-flop becomes reset. For purposes of the present discussion, arelatively high signal, such as V +6 volts, represents binary 1 and arelatively low signal, such as ground, represents binary 0 (othersuitable voltages may, of course, be used instead).

The logic circuit includes an OR gate 16, twoAND gates 18 and 20, and aNOR gate 22. OR gate 16 receives the complementary signal A produced byinverter 24 and 6 signal produced by flip-flop 12. AND gate 18 receivesthe 6 signal produced by flip-flop l0 and the B signal producedby ORgate 16. AND gate 20 receives the signals A and Q NOR gate 22 receivesthe signal C produced by AND gate 18 and the signal E produced by ANDgate 20. NOR-gate 22 connects t the data terminal D of flip-flop 12.

The single-pole, single-throw switch, which at the instant of closureproduces noise due to contact bounce,

is shown at 25. It connects to the data terminal D of flip-flop 10. AnN-type MOS transistor 26 is connected at its drain electrode 28 to thedata terminal D and at its source electrode 30 to a reference voltagesource such as ground. The gate electrode 32 of this transistor connectsto the voltage source +V As connected, the transistor operates as a loadresistor, as discussed briefly below.

As already mentioned, the clock signal dz is applied to the triggerableflip-flop 10. Inverter 34 applies the complement (b of this clock signalto the trigger terminal of flip-flop 12.

In the discussion of the operation of the circuit of FIG. 1 whichfollows, both FIGS. 1 and 2 should be referred to. The field-effecttransistor 26 is normally biased on by the positive voltage applied toits gate electrode. Accordingly, a conduction path exists between thedrain 28 and source 30 electrodes. The design of this transistor issuchv that the conduction path impethat the switch arm is in actualcontact with the switch 2 terminal, the voltage at A is pulled up to'Veach interval that the switch 26 is open, the voltage at A is pulledback down to ground through transistor 26. The positive swings of thevoltage are sufficient, if present at D, when the positive-going leadingedge of the clock signal occurs, to set flip-flop l0.

Assume now that at time t (FIG. 2) during one of the positive excursionsof A, the leading edge 50 of clock signal 4) occurs. This causes theflip-flop 10 to become set so that 6 changes to 0. This disables ANDgate 18, changing C to 0. The positive-going edge 50 of the wave 4) hasno effect on flip-flop 12 because inverter 34 inverts this signal sothat it appears as a negative-going edge to the flip-flop 12.

' A signal at A is inverted at 24 and the complementary signal A servesas one'input to AND gate 20. The second signal applied to AND gate 20 isthe signal 6 which, at time t is equal to i This signal therefore,serves as a priming signal to AND gate 20. Now, each time the signal Agoes relatively negative, representing a 0, A- goes positive,representing a l and AND gate 20 becomes enabled and each time thesignal A goes positive, A represents a 0 and AND gate 20 becomesdisabled. The signal E thereby produced is an oscillation which iscomplementary to the oscillation A. A s-C=O, each time E represents a 0,a l is applied to the D terminal and each time the signal E represents al, a O is applied to the D terminal. This oscillating signal is shown atD in FIG. '2. During. the period between t and the time just before thisoscillating signal, if present, has no effect on the second flip-flop 12in view of the absence of the positive-going edge of the clock signal(I).

At time t,, which is one-half period of the clock signal ()5 later thanthe time the first flip-flop 10 was set, it may be assumed thatoscillations due to switch bounce have died down. Immediately before t'was still 1. After switch bounce has died down, A 1 so that Ff= 0. Thus,A ND gate 20 is disabled.As previously mentioned, Q, O (flip-flop isset) so that AND gate 18 also is disabled. Thus, C E 0,-enabling NORgate 22 so that D 1. At time t,, (it goes negative so that a goespositive. This positive-going signal triggers flipflop 12 and the latterbecomes set. The output signal Q 1 serves as the input to the circuit itis desired to actuate. One application for this circuit is in thetimesetting control for an integrated circuit watch. However, this isjust one example of the use of the circuit.

When flip-flop 12 becomes set, 6 changes to 0. This signal maintains ANDgate disabled so that E=O. As flip-flop 10 also is set, 6 O and AND gate18 is disabled. Thus C= 0. Accordingly, NOR gate 22 is locked in theenabled state; D remains l and the clock signal $does not distrub theset state of flip-flop 12. This condition remains so long as switch 25stays closed.

In the explanation above of the operation of the circuit, the assumptionwas made that at time t a positivegoing peak of the oscillation waspresent at A. This need not be the case. If, instead, a negative-goingoscillation is present, then the positive going edge 50 of the clocksignal (I) will cause the first flip-flop 10 to remain in the resetcondition. If flip-flop 10 remains reset, the second flip-flop 12 nevercan become set. With flipflop 10 reset, Q, l, priming AND gate 18. 6also is l, enabling OR gate 16. Thus, B I so that AND gate 18 is enabledand C remains 1. If C remains 1, D remains 0 and flip-flop 12 remainsreset.

Under the circumstances above, the flip-flop 10 will not become setuntil time t which is one complete period of the clock signal after timet assuming that between times t and t the oscillations due to switchbounce have ceased. In the present application, the delay which resultsis no particular disadvantage. For example, if the frequency of d) isHz, the delay of 1 period is only 1/30 of a second.

In the foregoing explanation, it was also assumed that at time 1 theoscillations had died down. If not, the circuit still can operate. If attime t,, flip-flop 10 already is set but A is relatively negative due toa negativegoing swing in the oscillations which still may be present,A 1. 6 1 so that E 1. Therefore, D 0 and flip-flop 12 does not becomeset at time But, one complete period of the clock signal later, theoscillations surely should have died out and at that time, flipflop 12will become set.

However, if flip-flop I0 is set at time t and at time t, oscillationsare still present and A is 1, then flip-flop 12 will become set. Thismeans that the oscillations have been interpreted as a data signal andthis may not be a valid assumption. For this reason, it is preferredthat the frequency of the clock signal be chosen so that in onehalf-period of the clock after flip-flop 10 has been set, theoscillations have died down.

It may also sometimes occur in other applications of this circuitmentioned later, that the flip-flop 10 is set by noise not followed byany signal. That is, after a short burst of noise present at node Aduring which the clock signal (i) sets flip-flop 10, A returns to O. Inthis case, assuming the burst has died out within a half period of theclock signal, flip-flop 12 does not become set. Oneperiod of the clocksignal after flip-flop 10 is set, the clock signal resets flip-flop 10.Thus, this noise burst produces no output signal at Q fluctuations onthe line.

When the switch 25 is opened, both flip-flops l0 and 12 shortly becomereset. The operation should be clear from what has already beendiscussed. In brief, A changes to 0 and when the positive-going leadingedge, such as 50, of the clock signal :15 occurs, flip-flop 1013ccomesreset. This primes AND gate 18. The signal A 1 enables OR gate 16 sothat B 1. Thus, AND gate 18 places a 1 at C of NOR gate 22 so that D:equals 0.

Now, when a negative-going edge such as S1 of wave 4) occurs, goespositive and flip-flop 12 is reset.

In a number of applications of the present invention, it is important tobe able to use a single-pole, singlethrow switch such as 25. Such aswitch is of simple mechanical design and can be made of sufficientlysmall size to fit the space available in a small case such as might beused for an electronic wrist watch. Were it permitted to use, forexample, a single pole, doublethrow switch, other simpler logic designsare possible.

It should be mentioned that while the present circuit is illustrated asone especially suitable for eliminating the harmful effect of switchbounce, it is also useful in other applications. For example, inautomobile clock applications, especially those employing relativelylong lines for carrying a time setting signal from a switch which is notphysically close to the time setting input of the clock, noise often isa problem. The line may pass'through environments in which there is highambient noise due to switching of high voltages, for example, and thefields due to'these voltages induce noise signals on the lines. In theseapplications, just as in the I one described, it is necessary to havesome means available for providing a positive indication of the presenceof signal while discriminating against noise. This means is the samecircuit shown in FIG. 1.

The circuit is also useful in certain automatic test systems where noswitch such as 25 is present. Instead, node A may be tied to a long linewhich passes through a high electrical noise environment and in which itis necessary to distinguish a change in the direct voltage terminal, atrigger terminal'and an output terminal;

a logic circuit including first gate means normally primed by said firstflip-flop, second gate means normally primed by said second flip-flopand third gatemeans driven by said first and second gate means andcoupled at its output terminal to the data terminal of the secondflip-flop, said third gate means being enabled only when both the firstand second gate means are disabled;

an input line for carrying a direct current level signal it is desiredto detect and for sometimes also carrying noise, coupled to the dataterminal of said first flip-flop and also to said first and second gatemeans, the latter in a sense to disable both gate means when signal ispresent and to enable both gate means when signal is not present; and

means for applying a clock signal to the trigger terminal of said firstflip-flop and its complement to the trigger terminal of said secondflip-flop.

2. In the combination as set forth in claim 1, said first and secondgate means each comprising an AND gate and said third gate meanscomprising a NOR gate.

3. In the combination as set forth in claim 2, further includinginverter means, said input line being coupled to said first and secondgate means via said inverter means.

4. A circuit for sensing the presence of a direct current level signalon an input line preceded by noise on said line comprising, incombination:

first gate means;

means responsive to the noise on said line preceding said signal fordisabling said first gate means; second gate means;

means responsive to the signal on said line following said noise fordisabling said second gate means; and

means responsive to a control signal produced a given interval of timeafter said first gate means is disabled, said interval beingchosen'normally to be sufficient to permit the noise to dissipate andthe given time interval and to a second control signal, for

enabling said first gate means.

6. A circuit as set forth in claim 5, wherein said two control signalsare complementary signals.

7. A circuit as set forth in claim 4, wherein said means responsive tonoise on said line comprises a first flip-flop.

8. A circuit as set forth in claim 7, said means responsive to a controlsignal including a second flip-flop.

9. A circuit as set forth in claim 7, said means responsive to saiddisabled condition of said first and second gate means comprising a NORgate.

10. A circuit for sensing the presence of a direct current levelinformation signal on an input line preceded by noise on said linecomprising, in combination:

means responsive to a first control signal and to the noise on said linepreceding said information signal for producing and storing a firstsignal; and

means responsive to the stored first signal, to the presence of theinformation signal on said line following said noise and to a secondcontrol signal following the first control signal by an interval At, forproducing and storing a second signal, this one indicative of saidinformation signal on said line, where At is an interval which isnormally sufiicient to permit the noise to dissipate and the signal, ifpresent, to appear. I

11. A circuit as set forth in claim 10, further including meansresponsive to the recurrence of said first control signal during a timeinterval after said second control signal has terminated, and to theabsence of signal on said line, for removing said first signal.

1. In combination: first and second flip-flops, each having a data inputterminal, a trigger terminal and an output terminal; a logic circuitincluding first gate means normally primed by said first flip-flop,second gate means normally primed by said second flip-flop and thirdgate means driven by said first and second gate means and coupled at itsoutput terminal to the data terminal of the second flip-flop, said thirdgate means being enabled only when both the first and second gate meansare disabled; an input line for carrying a direct current level signalit is desired to detect and for sometimes also carrying noise, coupledto the data terminal of said first flip-flop and also to said first andsecond gate means, the latter in a sense to disable both gate means whensignal is present and to enable both gate means when signal is notpresent; and means for applying a clock signal to the trigger terminalof said first flip-flop and its complement to the trigger terminAl ofsaid second flip-flop.
 2. In the combination as set forth in claim 1,said first and second gate means each comprising an AND gate and saidthird gate means comprising a NOR gate.
 3. In the combination as setforth in claim 2, further including inverter means, said input linebeing coupled to said first and second gate means via said invertermeans.
 4. A circuit for sensing the presence of a direct current levelsignal on an input line preceded by noise on said line comprising, incombination: first gate means; means responsive to the noise on saidline preceding said signal for disabling said first gate means; secondgate means; means responsive to the signal on said line following saidnoise for disabling said second gate means; and means responsive to acontrol signal produced a given interval of time after said first gatemeans is disabled, said interval being chosen normally to be sufficientto permit the noise to dissipate and the signal, if present, to appear,and to the disabled condition of both said first and said second gatemeans, for indicating that a signal is present on said line.
 5. Acircuit as set forth in claim 4, further including means responsive tothe absence of signal after said given time interval and to a secondcontrol signal, for enabling said first gate means.
 6. A circuit as setforth in claim 5, wherein said two control signals are complementarysignals.
 7. A circuit as set forth in claim 4, wherein said meansresponsive to noise on said line comprises a first flip-flop.
 8. Acircuit as set forth in claim 7, said means responsive to a controlsignal including a second flip-flop.
 9. A circuit as set forth in claim7, said means responsive to said disabled condition of said first andsecond gate means comprising a NOR gate.
 10. A circuit for sensing thepresence of a direct current level information signal on an input linepreceded by noise on said line comprising, in combination: meansresponsive to a first control signal and to the noise on said linepreceding said information signal for producing and storing a firstsignal; and means responsive to the stored first signal, to the presenceof the information signal on said line following said noise and to asecond control signal following the first control signal by an intervalDelta t, for producing and storing a second signal, this one indicativeof said information signal on said line, where Delta t is an intervalwhich is normally sufficient to permit the noise to dissipate and thesignal, if present, to appear.
 11. A circuit as set forth in claim 10,further including means responsive to the recurrence of said firstcontrol signal during a time interval after said second control signalhas terminated, and to the absence of signal on said line, for removingsaid first signal.